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Direct register access control of McBSP ARM interface on Overo Water +TOBI - SOLVED

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Direct register access control of McBSP ARM interface on Overo Water +TOBI - SOLVED

Nicola

This is one way for direct-register access control of the McBSP 3 ARM interface of the Gumstix Overo Water.
 I mounted the Gumstix on a TOBI board for connections.
 I haven't recompiled the kernel or touched the setup files or
 the pre-existing drivers... nothing of this.
This is my recipe:
1) install on a formatted SD card the stable Gumstix armstrong linux version
  ( see http://gumstix.org/get-started/how-to.html )
2) connect your Overo Water + Tobi system on Internet by LAN cable
3) connect the Gumstix to your windows PC by the USB cable and by the software putty.exe,
   open a control windows
    selecting an emulated serial connection (see putty instructions)
3) Check the internet link, use ( on the Gumstix )
   ifconfig eth1 192.168.0.5 netmask 255.255.255.0
   or whatever the desired IP address+netmask for connecting the Gumstix @ your router    
 4) install the C cross compiler :
   $ echo 'src/gz angstrom-base http://www.angstrom-distribution.org/feeds/unstable/ipk/glibc/armv7a/base'  > /etc/opkg/angstrom-base.conf
   $ opkg update
   $ opkg install task-native-sdk
 or better use
   $ opkg update
   $ opkg install task-native-sdk
 for updating all the software.
5) Reboot the gustix
6) Put the following code on your home directory ( or wherewer you prefer ) editing it with
    VI main.c
 or with any other any other editor you like. I use normally Eclipse for editing my software
 on the PC and transferring
 it to the remote system (the Gumstix) ( contact me if you want more info on this);
 I called the file "main.c" ; compile it using the command
  $ gcc -o main main.c
 and execute it using
  $ ./main

I setted the McBSP3 on the Overo Water module for driving a fast ADC converter.
The interface generates a free running clock of 20 or 40 MHZ and a Frame Sinc
signal every 20 clocK cicles. The Tx & Rx buffer are setted @ 20 bits .
Following the comments on each line, it is easily
possible to change all the McBSP3 settings to obtain the desired setup.
Many lines starts with a comment: those are the points to insert other settings
that I haven't used. See
  http://www.gumstix.org/hardware-design/overo-coms/74-overo-connectors/97-gumstix-overo-series-40-pin-header.html
for the TOBI connector pinout.
That's all!
Here's the code.
Nicola


#include <stdio.h> 
#include <fcntl.h>     
#include <sys/mman.h>   

#define CM_IVA2_BASE 0x48004000
#define CM_CORE_BASE 0x48004A00 // Clock distribution
#define CM_FCLKEN1_CORE_OFFSET 0x0  
#define CM_ICLKEN1_CORE_OFFSET 0x10  
#define CM_PER_BASE 0x48005000
#define CM_FCLKEN_PER_OFFSET 0x0    
#define CM_ICLKEN_PER_OFFSET 0x10    

#define SCM_INTERFACE_BASE 0x48002000 // Pad function definition
#define SCM_PADCONFS_BASE 0x48002030
#define SCM_PADCONFS_BASE_OFFSET 0x30 //  offset SCM_INTERFACE_BASE
#define SCM_GENERAL_BASE 0x48002270
#define SCM_GENERAL_BASE_OFFSET 0x270 //  needed for McBSP3
#define CONTROL_DEVCONF1_OFFSET 0x68 // needed for McBSP3
#define CONTROL_PADCONF_OFF_OFFSET 0x0  // offset SCM_GENERAL_BASE
#define CONTROL_MSUSPENDMUX_5_OFFSET 0x34 // offset SCM_GENERAL_BASE

 
#define CONTROL_PADCONF_UART2_CTS_OFFSET 0x144 //
#define CONTROL_PADCONF_UART2_TX_OFFSET 0x148  //
#define CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13C  // offset SCM_PADCONFS_BASE
#define CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140


#define McBSP3_BASE 0x49024000
#define McBSP3_MCBSPLP_SPCR1_REG_OFFSET 0x14
#define McBSP3_MCBSPLP_SPCR2_REG_OFFSET 0x10
#define McBSP3_MCBSPLP_PCR_REG_OFFSET 0x48
#define McBSP3_MCBSPLP_RCR1_REG_OFFSET 0x1C
#define McBSP3_MCBSPLP_RCR2_REG_OFFSET 0x18
#define McBSP3_MCBSPLP_XCR1_REG_OFFSET 0x24
#define McBSP3_MCBSPLP_XCR2_REG_OFFSET 0x20
#define McBSP3_MCBSPLP_SRGR1_REG_OFFSET 0x2C
#define McBSP3_MCBSPLP_SRGR2_REG_OFFSET 0x28
#define McBSP3_MCBSPLP_DXR_REG_OFFSET 0x8
#define McBSP3_MCBSPLP_DRR_REG_OFFSET 0x0
#define McBSP3_MCBSPLP_SYSCONFIG_REG_OFFSET 0x8C
#define McBSP3_MCBSPLP_XCCR_REG_OFFSET 0xAC
#define McBSP3_MCBSPLP_RCCR_REG_OFFSET 0xB0

#define MAP_SIZE (volatile unsigned long) 4*1024
#define MAP_MASK (volatile unsigned long)( MAP_SIZE - 1 )

/****************************************************************************************
                             COMMON VARIABLES DEFINITION
 ****************************************************************************************/
#define u32 volatile unsigned long
u32 *A;
u32 *B;
u32 *C;
unsigned long i;

/****************************************************************************************
                             LOCAL FUNCTIONS PROTOTYPES
 ****************************************************************************************/
void Clock_distribution_init(void);
void IO_pad_configuration(void);
void McBSP_3_init(void);

/****************************************************************************************
                                  LOCAL FUNCTIONS
 ****************************************************************************************/
int main(void){
  Clock_distribution_init();
  IO_pad_configuration();
  McBSP_3_init();

  fd = open("/dev/mem", O_RDWR | O_SYNC);
            if (fd < 0) {printf("Could not open file\n"); return;}
            C = (u32 *) mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, McBSP3_BASE & ~MAP_MASK);
            if (C<=0) {printf("Mapping failed\n"); close(fd); return;}
// reads something
  if (*(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR1_REG_OFFSET) && 0x00000002)// data ready for RX, needs C pointer to McBSP3_BASE
  printf("info_reg_RX: 0x%08x\n",*(u32 *)((u32)C+McBSP3_MCBSPLP_DRR_REG_OFFSET)  ); // needs C pointer to McBSP3_BASE
// writes something
 *(u32 *)((u32)C+McBSP3_MCBSPLP_DXR_REG_OFFSET)|=0xbbbbbbbb;
 *(u32 *)((u32)C+McBSP3_MCBSPLP_DXR_REG_OFFSET)&=0x00000000;
close(fd);
}


void Clock_distribution_init(void){
        // clock distribution
        int fd;
          fd = open("/dev/mem", O_RDWR | O_SYNC);
          if (fd < 0) {printf("Could not open file\n"); return;}
          B = (volatile unsigned long*) mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, CM_IVA2_BASE & ~MAP_MASK );
          if (B<=0) {printf("Mapping failed\n"); close(fd); return;}
           *(u32 *)((u32)B+CM_CORE_BASE_OFFSET+CM_ICLKEN1_CORE_OFFSET)|= 0x00000040; //enable PMAPCTRL clock System Control Module
          close(fd);
          fd = open("/dev/mem", O_RDWR | O_SYNC);
          if (fd < 0) {printf("Could not open file\n"); return;}
          B = (volatile unsigned long*) mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, CM_PER_BASE & ~MAP_MASK );
          if (B<=0) {printf("Mapping failed\n"); close(fd); return;}
           *(u32 *)((u32)B+CM_FCLKEN_PER_OFFSET)|= 0x00000002; // enable McBSP_3 FCLK pin1=1,GPIO_6 clock pin17=1  functional clock
           *(u32 *)((u32)B+CM_ICLKEN_PER_OFFSET)|= 0x00000002; // enable McBSP_3 CM_ICLK  Interface clock, Peripheral ICLK clock enable
          close(fd);
          fd = open("/dev/mem", O_RDWR | O_SYNC);
          if (fd < 0) {printf("Could not open file\n"); return;}
          B = (volatile unsigned long*) mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, SCM_INTERFACE_BASE & ~MAP_MASK );
          if (B<=0) {printf("Mapping failed\n"); close(fd); return;}
          *(u32 *)((u32)B+SCM_GENERAL_BASE_OFFSET+CONTROL_PADCONF_OFF_OFFSET)   &= 0xfffffffe; // SET PAD configuration possible
          *(u32 *)((u32)B+SCM_GENERAL_BASE_OFFSET+CONTROL_DEVCONF1_OFFSET)      &= 0xfffffffe; // enable McBSP_3 clock source as PRCM
          *(u32 *)((u32)B+SCM_GENERAL_BASE_OFFSET+CONTROL_MSUSPENDMUX_5_OFFSET) &= 0xfffffff1; // no suspend allowed for McBSP3
          close(fd);
}// end of Clock_distribution_init

void IO_pad_configuration(void){
        int fd;
          // Set GPIO for desired IO pins
          /********* McBSP_3 *********/
           fd = open("/dev/mem", O_RDWR | O_SYNC); // memory handling
           if (fd < 0) {printf("Could not open file\n"); return;}  // check memory handling ok
           A = (u32 *) mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, SCM_INTERFACE_BASE & ~MAP_MASK); //attenzione ! interface non pad; pad ha un offset di 0x30
           if (A<=0) {printf("Mapping failed\n"); close(fd); return;} // just in case
           //Note: at the reset, all are in safe mode 0b111
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_MCBSP3_DX_OFFSET)   |= 0x00070007; // set safe mode
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_MCBSP3_CLKX_OFFSET) |= 0x00070007; // set safe mode
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) &= 0xfffffff8; // set mode 1 (0b001) on mcbsp3_dx pin ; enable pin for mcbsp3 TX function pag.778
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) |= 0x00000001;
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) &= 0xfff8ffff; // set mode 1 on mcbsp3_dr pin ; enable pin for mcbsp3 RX function
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) |= 0x00010000;
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET) &=  0xfffffff8; // set mode 1 on mcbsp3_clkx pin ; enable pin for mcbsp3 clock function pag.778
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET) |=  0x00000001;
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET) &=  0xfff8ffff; // set mode 1 on mcbsp3_fsx pin ; enable pin for mcbsp3 Frame Sinc TX function
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET) |=  0x00010000;
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET) |=  0x00000100; // set the input-enable-bit on clock pin for functionality, retiming pag.783,3021
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET) |=  0x01000000; // set the input-enable-bit on fsx pin for functionality, retiming pag.783,3021
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) &= 0x3fff3fff; // disable wakeup events
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET)  &= 0x3fff3fff; // disable wakeup events
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) &= 0xf9fff9ff; // disable OFFENABLE and OFFOUTENABLE
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET)  &= 0xf9fff9ff; // disable OFFENABLE and OFFOUTENABLE
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) |= 0x00180018; // enable pull up/down; set pull up
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET)  |= 0x00180018; // enable pull up/down; set pull up
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_CTS_OFFSET) &= 0xffefffef; // set pull down
           *(u32 *)((u32)A+SCM_PADCONFS_BASE_OFFSET+CONTROL_PADCONF_UART2_TX_OFFSET)  &= 0xffefffef; // set pull down
           printf("McBSP_3 PAD configuration done.\n");
           /********************/
           close(fd);
}// end of IO_pad_configuration


void McBSP_3_init(void){
        int fd;
         fd = open("/dev/mem", O_RDWR | O_SYNC);
          if (fd < 0) {printf("Could not open file\n"); return;}
         C = (u32 *) mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, McBSP3_BASE & ~MAP_MASK);
          if (C<=0) {printf("Mapping failed\n"); close(fd); return;}
        // Init sequence_Master_Mode
        /******************************************************************************************************************/
        /******************************************************************************************************************/
           *(u32 *)((u32)C+McBSP3_MCBSPLP_XCCR_REG_OFFSET)&=  0xfffff7ff; // bit11=0 XFULL CYCLE resetted
           *(u32 *)((u32)C+McBSP3_MCBSPLP_RCCR_REG_OFFSET)|=  0x00000800; // bit11=1 RFULL CYCLE resetted
           *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR1_REG_OFFSET)&= 0xfffffffe; //Set RRST bit0 to 0; reset the RX
           *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)&= 0xffffff7f; //Set FRST bit7 to 0; reset the frame-sync generator
           *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)&= 0xfffffffe; //Set XRST bit0 to 0; reset the TX
        /******************************************************************************************************************/
        /******************************************************************************************************************/
           //McBSP_3_RX_REG_Setup
            // reset RX, already done
            *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  &= 0xffffefff; // bit12=0 RIOEN; DR,FSR,CLKR and CLKS are serial pins and not GPIO
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCCR_REG_OFFSET) &= 0xffffffdf; // bit5=0 DLB; Digital Loop-back off
            *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR1_REG_OFFSET)&= 0xffff7fff; // bit15=0 ALB: Analog loop-back Mode disabled
            // Enable/Disable multi-channel selection
            *(u32 *)((u32)C+McBSP3_MCBSPLP_RCR2_REG_OFFSET) &= 0xffff7fff; // set bit15=0 RPHASE, Choose 1 Phase for Receive Frame
            *(u32 *)((u32)C+McBSP3_MCBSPLP_RCR1_REG_OFFSET) &= 0xffffff1f; // set bits7:5 RWDLEN1 word length for phase1
            *(u32 *)((u32)C+McBSP3_MCBSPLP_RCR1_REG_OFFSET) |= 0x00000060; //  0x00000060 set to 20 bits
            *(u32 *)((u32)C+McBSP3_MCBSPLP_RCR1_REG_OFFSET) &= 0xfffff8ff; // set bits14:8 RFRLEN1 number = 1 of words in phase1
            *(u32 *)((u32)C+McBSP3_MCBSPLP_RCR2_REG_OFFSET) &= 0xfffff8ff; // set bits14:8 RFRLEN2
            *(u32 *)((u32)C+McBSP3_MCBSPLP_RCR2_REG_OFFSET) &= 0xffffffe7; // set bits4:3 =00; MSB first; Set the Receive Reverse Mode
            //*(u32 *)((u32)C+McBSP3_MCBSPLP_RCR2_REG_OFFSET) |= 0x00000008; //  set LSB first
            // Set the Receive Data Delay
            // Set the Receive Interrupt Mode
            // Set the Receive DMA Mode
            // *** Set the Receive Frame-Synch Mode ***
             *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET) &= 0xffff7fff; // set bit15=0 GSYNC no frame sync by fsr pin
             //*(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|=  0x00008000; // set bit15=1 GSYNC; Tx and RX synchronously operating
             *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)&=  0xffff7fff; // set bit15=0 GSYNC
            // ***
            // Set the Receive Frame-Sync Polarity
            // Set the SRG Frame-Sync Period and Pulse width
            // Set the receive clock mode
            *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |= 0x00000100; // set bit8=1 CLKRM receiver clock mode, driven by internal SRG if MCBSPLP_XCCR_REG[5] DLB bit=0
            *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  &= 0xfffffffe; // set bit0=0; CLKRP RX Clock Polarity, RX data sampled on falling edge of CLKR
            // Set the SRG Clock Divide-Down Value
            // Set the SRG Clock Synchronization Mode
            // Set an SRG Clock Input
            // Set the SRG Input Clock Polarity
            //  *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)   &= 0xfffffffe; // set bit0=0; CLKRP RX Clock Polarity, RX data sampled on falling edge of CLKR
    /********************/
           //McBSP_3_TX_REG_Setup
            // reset TX, already done
            *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)&=   0xffffdfff; // bit13=0 XIOEN; DX,FSX,CLKX are serial port and not GPIO
            // Enable/Disable digital loop-back mode
            // Enable/Disable analog loop-back mode
            // Enable/Disable multi-channel selection
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCR2_REG_OFFSET) &= 0xffff7fff; // set bit15=0 XPHASE, Choose 1 Phase for Transmit Frame
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCR1_REG_OFFSET) &= 0xffffff1f; // set bits7:5 XWDLEN1 word length for phase1
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCR1_REG_OFFSET) |= 0x00000060; // set to 20 bits
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCR2_REG_OFFSET) &= 0xffffff1f; // set bits7:5 XWDLEN1 word length for phase1
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCR1_REG_OFFSET) &= 0xfffff8ff; // set bits14:8 XFRLEN1 number = 1 of words in phase1
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCR2_REG_OFFSET) &= 0xfffff8ff; // set bits14:8 XFRLEN2
            // Set the Transmit Reverse Mode
            *(u32 *)((u32)C+McBSP3_MCBSPLP_XCR2_REG_OFFSET) &= 0xfffffffc; // set bits1:0 XDATDLY to 00, Set the Transmit Data Delay
            // Set the Transmit DXENA Mode
            // Set the Transmit Interrupt Mode
            // Set the Transmit DMA Mode
            // *** Set the Transmit Frame-Synch Mode pag.3042 ***
             *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|=  0x00001000; // set bit12=1 FSGM SRG transmit frame synchronization mode
             *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |=  0x00000800; // set bit11=1 FSXM TX Frame synch mode by SRG
            // ***
            *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  &=  0xfffffff7; // set bit3 Transit Frame-Sync Polarity; =0 -> active high
            // Set the SRG Frame-Sync Period and Pulse width
            //already done,set the Transmit Clock Mode // *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |=  0x00000200; // set bit9=1  CLKXM => TX clock mode,Tx clock driven by internal SRG and mbsp3_clkx is output, set the Transmit Clock Mode
            *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)   &= 0xfffffffd; // set bit1=0; CLKXP TX Clock Polarity, TX data driven on rising edge of CLKX
            //*(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |=  0x00000002; // set bit1=1 CLKXP; clock polarity of Tx
            // Set the SRG Clock Divide-Down Value
            // Set the SRG Clock Synchronization Mode
            // Set an SRG Clock Input
            // Set the SRG Input Clock Polarity
    /********************/
           //McBSP_3_SRG_REG_Setup _ SAMPLE RATE GENERATOR
            // SRG Reg Setup
             *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)&= 0xffffffbf; //Set SGR rst bit6 to 0; reset the SGR, Sample Rate Generator
             while ( (*(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET) & 0x00000040)!=0 ); // waits bit6,GRST become 0;
       //pre-setup
             //reset RX already done
             //reset TX already done
             //SPCR1 bit7 DX enabler;bit0 RX reset pag 3059
             //SPCR2 bit9=1 free running mode; bit7 frame sync generator reset; bit6 sample rate generator reset; bit0 TX reset
               *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|=  0x00001000; // set bit12=1 FSGM SRG transmit frame synchronization mode; FUNDAMENTAL!!!!
          // MODULE CONFIGURATION : Master RX & TX
              *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |= 0x00000100; // set bit8=1 CLKRM receiver clock mode, driven by internal SRG; needed for FRS_int frame-sync from FSG
              *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |= 0x00000200; // set bit9=1 CLKXM => TX clock mode,Tx clock driven by internal SRG
              *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |= 0x00000400; // set bit10=1 FSRM receive frame synch mode, driven by internal SRG; needed for FRS_int frame-sync from FSG
              *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  |= 0x00000800; // set bit11=1 FSXM TX Frame synch mode by SRG____ NEEDED FURTHER
              // end MODULE CONFIGURATION
                  *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)&=  0xffffbfff; // set CLKSP bit14=0 ; clock polarity rising edge
                  //*(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|=  0x00004000; // set CLKSP bit14=1 ; clock polarity falling edge
           //end pre-setup
                 // clock sourse select for SRG
             *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|= 0x00002000; // Set CLK_SM bit13 and SCLK_ME bit7 as 1 and 0  respectively for McBSP3_ICLK clock as input clock sample rate generator,to set the SRG input clock @ McBSPI3_ICLK
             *(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  &= 0xffffff7f; // set SCLME bit7 to set the SRG input clock @ McBSPI3_ICLK
             //*(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)&= 0xffffdfff; // Set CLK_SM bit13 and SCLK_ME bit7 as 0 and 0  respectively for McBSP3_FCLK clock as input clock sample rate generator
             //*(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET)  &= 0xffffff7f;
              if ( (*(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET) & 0x00002000) ==0 ) {// checks CLKSM bit13 = 0, and it should not!
            *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)&= 0xffff7fff; // set bit15=0 GSYNC no frame sync by fsr pin ; CLKG free running
            //*(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|= 0x00008000; // bit15=1 GSYNC; sample rate generator in sync with frame
            if ((*(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET) & 0x00008000)==0) // check GSYNC bit15,Sample Rate Generator Synch; if =0 SRG clock if free running
            *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|=0x00000014; // config SRGR2_REG bits11:0 FPER, frame period duration in CLKG units;0x14=20 clks
              } else {
              if((*(u32 *)((u32)C+McBSP3_MCBSPLP_PCR_REG_OFFSET) & 0x00000800)==1) // checks PCR_REG bit11, TX FSXM bit; if 1,frame sync derived by FSGM in SRGR2
               *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|=0x00001000;// Config SRGR2_REG bit12, FSGM bit; Transmit frame sync signal driven by SRG frame sync signal,ie FSG
               //*(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)&=0xffffefff;// Config SRGR2_REG bit12, FSGM bit; Transmit frame sync signal driven by TX buffer=empty condition
                  *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)&=  0xfffff000; // set FPER bits0:11 = 20 or 40 ,Frame period duration, in CLKG units
                  *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR2_REG_OFFSET)|=  0x00000014; // set to 20
                  }
              *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR1_REG_OFFSET)&= 0xffff00ff;// config SRGR1_REG pin15:8 FWID; Frame Width+1= pulse duration ; if 0, duration=1
              *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR1_REG_OFFSET)&= 0xffffff00;// config SRGR1_REG pin 7:0 CLKGDV Sample Rate Generator clock divider =1
              *(u32 *)((u32)C+McBSP3_MCBSPLP_SRGR1_REG_OFFSET)|= 0x00000003;// 1 -> 41,5 MHz; 3->20,75 MHz
              // clock sourse select for SRG
              for(i=1;i<=40;i++); // waits 2 CLKSRG cycles
             // end of SRG Reg Setup
        /******************************************************************************************************************/
        /******************************************************************************************************************/
        // setup the data acquisition register
          *(u32 *)((u32)C+McBSP3_MCBSPLP_DXR_REG_OFFSET)|= 0x00000000;// NB ! config the acuisition / TX register DXR_REG
        // end of data acquisition register setup
        /******************************************************************************************************************/
        /******************************************************************************************************************/
          *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR1_REG_OFFSET)|= 0x00000001;// set the SPCR1_REG bit0 RRST to 1; enable the RX
          *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)|= 0x00000001;// set the SPCR2_REG bit0 XRST to 1; enable the TX
        /******************************************************************************************************************/
        /******************************************************************************************************************/
          // if the internally generated frame-sync required
           *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)|= 0x00000080;// set the SPCR2_REG bit7 FRST to 1; enable the Frame Sync
        //  *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)|= 0x00000040; //Set SGR grst bit6 to 1; un-reset the SGR, Sample Rate Generator
           for(i=1;i<=40;i++); // waits 2 CLKSRG cycles
        // un-resetting
           *(u32 *)((u32)C+McBSP3_MCBSPLP_SPCR2_REG_OFFSET)|= 0x00000040; //Set SGR grst bit6 to 1; un-reset the SGR, Sample Rate Generator
        //   *(u32 *)((u32)C+McBSP3_MCBSPLP_XCCR_REG_OFFSET)|=  0x00000800; // bit11=1 XFULL CYCLE un-resetted
        //   *(u32 *)((u32)C+McBSP3_MCBSPLP_RCCR_REG_OFFSET)&=  0xfffff7ff; // bit11=0 RFULL CYCLE un-resetted
           for(i=1;i<=40;i++); // waits 2 CLKSRG cycles
        close(fd);
        printf("McBSP_3 pointers to memory are ok\n") ;
}// end of procedure void McBSP_3_init(void)
/******************************************************************************************************************/

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Re: Direct register access control of McBSP ARM interface on Overo Water +TOBI - SOLVED

bhamadicharef
"fast ADC converter" can you give some example ?
Any schematics to study ?

Thank you

Brahim
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Re: Direct register access control of McBSP ARM interface on Overo Water +TOBI - SOLVED

Nicola
Hi brahim. Sorry but I cannot give schmatics...I'm working on a very big project granted by an important european research center and I must respect very strict rules about intellectual properties. however, I may syggest you to look for Texsas Instruments ADC and/or DAC converters that are well suited to be connected and managed by
McBSP whom Gumstix CPU are equipped with. Take care of the voltage swing of the signals : 0-1.8V on the Gumstix and 0-3.3 or 0-5 volts on external hardwares: you should also use a level converter.
Nicola
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Re: Direct register access control of McBSP ARM interface on Overo Water +TOBI - SOLVED

bhamadicharef
I understand you ... my curiosity was more about the "fast"
You mean few kHz sampling ? (e.g. audio 48kHz), few 100 kHz sampling ? (e.g. pro audio 192k)
or few MHz sampling ? 10 MHz sampling ? 10 MHz sampling ? for some scientific data ?

Brahim
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Re: Direct register access control of McBSP ARM interface on Overo Water +TOBI - SOLVED

Nicola
Considering the interface speed ( roughly 40 MHz maximum) you can think about the acquisition of
signals up to 1 or 2 Msps to maintain granular noise "under control".... the maximum rate you shuold
acquire (in terms of frequency spectrum limits) is given by the Nyquist theorem or the Sampling theorem.
Nicola
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